The capability of integrating analog, digital, high voltage, and high power functionality in a single technology has been important in the design of various electronic systems. For example, smart power BCD (Bipolar Complementary metal-oxide semiconductor (CMOS) Diffusion metal-oxide semiconductor (DMOS)) technology has been widely used in various high power applications such as automotive electronic systems. This may be due to an ease of integrating a laterally diffused metal oxide semiconductor device (LDMOS) in a Bipolar CMOS (BiCMOS) process flow. A Reduced Surface Field (RESURF) technique has been typically used to optimize device performance and has allowed for the integration of high voltage devices with bipolar and MOS transistors. However, as MOS devices are adapted for high voltage applications, problems arise with respect to high on-state resistance issue. In the LDMOS device, when a high voltage is applied to the gate, an electrical channel under the gate structure has a higher on-state resistance and low saturation current. As a result, the LDMOS power transistor's performance is degraded. One approach to improve on-state resistance is to utilize variation of lateral doping for a drift region in a junction isolation technology. Although this approach has been satisfactory for its intended purpose, it has not been satisfactory in all respects. Therefore, what is needed is a new and improved high voltage device that has a reduced on-state resistance.